The disclosure relates to polishing compositions for modifying the removal rate of silicon oxide-containing layers in semiconductor devices. It also relates to chemical mechanical planarizing (CMP) processes for removing silicon oxide-containing layers from underlying layers, such as SiC, SiCN, Si3N4 or SiCO.
Chip fabricators use multiple chemical-mechanical-planarization (CMP) steps to planarize wafers to facilitate the production of flat substrate surfaces. These flat surfaces facilitate the production of multi-level integrated circuits without the detrimental distortion experienced from applying dielectric to uneven substrates.
The CMP process is typically carried out in a two-step sequence to improve polishing performance. First, the polishing process uses a “first-step” slurry specifically designed to rapidly remove the interconnect metal, such as copper. After this initial copper removal step, a “second-step” slurry removes the barrier layer. Typically, the second-step slurries have selectivity to remove the barrier layer without adversely impacting the physical structure or electrical properties of the interconnect structure by “dishing” the interconnect metal. The removal rate of the barrier versus the removal rate of the metal interconnect or the dielectric layer is known as the selectivity ratio. For purposes of this specification removal rate refers to a removal rate as change of thickness per unit time, such as, Angstroms per minute.
After removing the barrier layer, the slurry typically removes an underlying layer, such as a silicon oxide-containing material. For the purposes of this invention, silicon oxide-containing materials include materials derived from silanes such as tetratethylorthosilicate (TEOS) and other silicon oxide-containing coatings used to fabricate semiconductors other than SiCO or SiOC. Unfortunately, slurries that remove silicon oxide-containing materials at rapid removal rates tend to also remove underlying masks, caps, anti-reflective coatings and dielectrics, especially low k and ultra-low k dielectrics at unacceptable removal rates. The uncontrolled removal of these underlying layers can have a detrimental impact upon the integrated circuit's ultimate performance.
CMP polishing compositions have included alcohol amines for copper removal formulations. For example, Steckenrider et al., in U.S. Pub. No. 20020032987, disclose a metal polishing composition having a pH of 9 to 10.5, which contains an alcohol-amine. This composition has a polysilicon to insulating layer selectivity of greater than 100. These polishing compositions, however, utilize abrasive particles having sizes greater than or equal to 400 nanometers and do not display the requisite selectivity with respect to silicon oxide-containing layers, such as TEOS mask layers.
In several low k dielectric and ultra-low k integration schemes, depositing capping materials on top of the dielectrics protects the dielectrics from mechanical damage. Then above the capping layer a mask layer, such as TEOS, defines area for dielectric or interconnect metal within the integrated circuit by removing the mask layer with a patterned etch process. After etching, a barrier layer covers the substrate and then a metal layer, such as copper, fills the channels or vias. For efficacious CMP, these semiconductor integration schemes typically require the selective removal of mask layers, such as TEOS mask layers with low-level dishing of metal interconnects and minimal removal of a bottom capping layer. For some integrations schemes, however, it is advantageous to also remove the lower capping layer and stop on the low k dielectric.
Since silicon oxide-containing layers, such as TEOS, have higher dielectric constants than the low k and ultra-low k materials, it is advisable to keep these TEOS layers as thin as possible to maintain the wafer's low-effective dielectric constant. Because thicker TEOS layers improve process control for CMP integration, however, the ultimate thickness selected represents a compromise between these two competing functions. The “thick” TEOS layers resulting from this compromise require polishing composition with an efficient mask removal step with a controlled interconnect metal removal rate.
In summary, these semiconductor integration schemes require the selective removal of silicon oxide-containing layers with an effective removal rate and either stopping on the lower capping layer or on the dielectric. In view of these considerations, there is a desire to provide polishing compositions that permit controlled silicon oxide-containing layer removal. In addition, there is an ongoing desire to remove silicon oxide-containing layers, such as TEOS mask layers, with reduced defectivity.
In addition, since semiconductor fabricators rely upon different integration schemes and low k/ultra-low k materials, semiconductor customers have different requirements for the CMP slurries. These divergent integration schemes render formulating a universal polishing solution most difficult. Thus it is also efficacious to adjust the removal rate of silicon oxide-containing layers, cap layers, as well as the metal interconnect, such as copper to satisfy multiple integration schemes.